VLSI Projects
S No IEEE Project Title Price Base Papers Screen Shorts Buy Project
1 2016 Design Of High Speed Multiplier Using Modified Booth Algorithm With Hybrid Carry Look-Ahead Adder 4000
2 2016 Design Of Low Power, High Performance 2-4 And 4-16 Mixed-Logic Line Decoders 4000
3 2016 High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels 4000
4 2016 Dual Use Of Power Lines For Design-For-Testability—A Cmos Receiver Design 4000
5 2016 Hybrid Lut/Multiplexer Fpga Logic Architectures 4000
6 2016 Input-Based Dynamic Reconfiguration Of Approximate Arithmetic Units For Video Encoding 4000
7 2016 Low-Cost High-Performance Vlsi Architecture For Montgomery Modular Multiplication 4000
8 2016 Fault Tolerant Parallel Ffts Using Error Correction Codes And Parseval Checks 4000
9 2016 Concept, Design, And Implementation Of Reconfigurable Cordic 4000
10 2016 A Method to Design Single Error Correction Codes With Fast Decoding for a Subset of Critical Bits 4000
11 2016 A High-Performance Fir Filter Architecture For Fixed And Reconfigurable Applications 4000
12 2016 Floating-Point Butterfly Architecture Based on Binary Signed-Digit Representation 4000
13 2016 Pre-Encoded Multipliers Based On Non-Redundant Radix-4 Signed-Digit Encoding 4000
14 2015 Reliable and Error Detection Architectures of Pomaranch for False-Alarm-Sensitive Cryptographic Applications 3000
15 2015 RECURSIVE APPROACH TO THE DESIGN OF A PARALLEL SELF-TIMED ADDER 2000
16 2015 A novel approach to realize Built-in-self-test(BIST) enabled UART using VHDL 3000
17 2015 LOW-POWER AND AREA-EFFICIENT SHIFT REGISTER USING PULSED LATCHES 3000
18 2015 High Speed Convolution And Deconvolution Algorithm Based On Ancient Indian Vedic Mathematics 3000
19 2015 RECURSIVE APPROACH TO THE DESIGN OF A PARALLEL SELF-TIMED ADDER 3000
20 2014 A Decimal / Binary Multi-operand Adder using a Fast Binary to Decimal Converter 2000
21 2014 Design and Development of FPGA Based Low Power Pipelined 64-Bit RISe Processor with Double Precision Floating Point Unit 2000
22 2014 Comments on “Self-Checking Carry-Select Adder Design Based on Two-Rail Encoding” 2000
23 2014 A Fully Static Topologically-Compressed 21-Transistor Flip-Flop With 75% Power Saving 2000

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